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AQA A-Level Computer Science

13.2.1 FSMs with and without output

Finite State Machines (FSMs) are abstract models used to simulate systems that transition between different states in response to inputs. They are fundamental in computing, particularly in the design of parsers, hardware controllers, and language recognisers.

What is a finite state machine?

A Finite State Machine is a computational model that consists of a limited number of states and a set of rules for moving from one state to another, depending on a sequence of inputs. The system can be in only one state at any given time, and transitions are triggered by input symbols from a defined alphabet.

FSMs are composed of the following core elements:

  • A finite set of states: The different configurations the system can be in.

  • An input alphabet: The set of valid input symbols (e.g. {0, 1} for binary strings).

  • A transition function: Rules that define which state to move to for each state/input pair.

  • An initial state: The starting state of the machine.

  • (Optional) A set of accepting or final states: States that determine whether an input string is accepted (for FSMs without output).

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FAQ

Non-deterministic FSMs (NDFSMs) differ from deterministic FSMs (DFSMs) in that they can have multiple possible transitions for the same input symbol from a single state. In contrast, DFSMs allow only one transition per input per state. Although the study of FSMs in this topic typically focuses on deterministic models, understanding non-determinism helps in conceptual clarity and algorithm design. For FSMs without output, non-determinism means that the machine accepts a string if at least one possible path leads to an accepting state. This allows for greater flexibility in pattern recognition. However, for FSMs with output, such as Mealy machines, non-determinism complicates the generation of a consistent output string since multiple transitions may produce different outputs. In practice, FSMs used in implementation are deterministic because they are easier to simulate and reason about. NDFSMs, however, are theoretically powerful, and any NDFSM can be converted into an equivalent DFSM that recognises the same language.

Mealy machines are widely used in real-world systems that require outputs based on transitions. One common application is in digital circuit design, particularly in creating synchronous sequential circuits where output depends on both the current state and the input, such as traffic light controllers or alarm systems. Mealy machines are also applied in network protocol design, where devices need to generate responses based on sequences of incoming messages—for example, interpreting TCP or HTTP message flows. In text parsing and data compression, Mealy machines can track symbol changes and encode them efficiently. Another practical area is in robotics and control systems, where a robot may adjust its behaviour (output) as it receives real-time sensor inputs (input), using a Mealy model to determine how to act. Because Mealy machines react immediately to inputs and can produce different outputs from the same state depending on the input, they are well-suited for responsive, real-time systems.

FSMs without output are ideal for validating input formats because they can determine whether an entire string meets a specific pattern or structure. These FSMs are typically used as recognisers that accept valid strings and reject invalid ones without producing any output. For example, an FSM can validate whether a binary number ends in 01, whether a sequence contains an even number of 1s, or whether a password meets character requirements. Their usefulness comes from the fact that accepting states act as final checks—the machine doesn't need to remember the entire input, only its current state. On the other hand, FSMs with output (e.g. Mealy machines) are not primarily used for validation, but for processing input and producing a result, such as transforming data or signalling actions. While they can be adapted to validation, the lack of a final accepting state model makes FSMs without output more straightforward and efficient for format checking tasks.

Loops and cycles play a critical role in FSM design because they allow machines to handle repetitive input patterns and extend their operation over inputs of arbitrary length. In FSMs without output, loops enable the machine to remain in a state or revisit a state while processing sequences that don’t affect the final result, such as repeated characters that do not influence acceptance. For instance, to recognise binary strings ending in 01, the FSM might loop on 1s in the initial state to ignore any leading 1s. In FSMs with output, loops also serve to manage repeated inputs but have a more active role—they generate output with each loop iteration. For example, a loop might continuously emit a 0 until a change in input triggers a different transition and output. Designers must ensure loops don’t lead to unintended behaviour, such as infinite non-productive cycles or incorrect output sequences, especially in machines used for real-time systems.

Yes, a Mealy machine can simulate the behaviour of an FSM without output by treating output generation as binary indicators of acceptance. In this case, instead of ending in an accepting state, the Mealy machine can be designed to emit a signal (such as 1) only if the transition would lead into what would be an accepting state in a recogniser FSM. Alternatively, the machine can generate 0 on all transitions and a 1 only when the last input causes the system to enter an equivalent accepting state. This approach requires careful transition design so that the final output correctly reflects whether the entire input string satisfies the condition. However, this method becomes complex if the decision of acceptance depends on the entire input string, not just the last few symbols. Hence, while possible, using a Mealy machine purely for recognition is generally less intuitive and efficient than using an FSM without output, which has a built-in mechanism for indicating acceptance via final states.

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