Signed binary using two’s complement allows both positive and negative integers to be represented in binary. It is efficient, logical, and essential for arithmetic operations in digital systems.
What is signed binary representation?
In binary systems, numbers are normally represented using unsigned binary, which means all bits are used to store values of non-negative integers only. However, this is limited — it doesn’t allow for representing negative values.
To represent both positive and negative integers, a system called signed binary representation is used. This involves using one of the bits to indicate the sign of the number. The most common and effective method is known as two’s complement representation.
Other methods like sign-and-magnitude and one’s complement exist, but two’s complement is preferred in most digital systems for several reasons, which are explored below.
Why is two’s complement preferred?
Two’s complement has several benefits over other signed binary systems:
Unique representation of zero: Unlike one’s complement, where both +0 and −0 exist, two’s complement has only one representation for zero, simplifying comparisons and arithmetic.
Practice Questions
FAQ
In two’s complement, the range of values for an n-bit system is from −2^(n−1) to 2^(n−1) − 1. This asymmetry exists because of how two’s complement encodes negative numbers. The most significant bit (MSB) acts as the sign bit and contributes a negative weight of −2^(n−1), while the remaining bits contribute positive values. Since zero must also be represented, and positive numbers start from 0 rather than 1, there ends up being one more negative number than positive. For example, in an 8-bit system, the range is −128 to +127. The binary pattern 10000000 represents −128, while the largest positive value, 01111111, is +127. There is no positive equivalent of −128 in this system. This design is intentional and allows for efficient binary arithmetic and logical consistency but results in the slight imbalance. It also means that trying to negate the minimum value (e.g. −128) causes overflow since +128 cannot be represented.
Taking the two’s complement of the minimum negative number in a given bit width causes overflow because its positive equivalent cannot be represented. In an 8-bit system, the minimum value is −128 (binary: 10000000). To find the two’s complement of this value (i.e. to negate it), you invert the bits (01111111) and add one, which gives 10000000 again. This is the same binary pattern, meaning the number stays as −128 instead of becoming +128. This outcome occurs because +128 does not exist in an 8-bit two’s complement range, which only goes up to +127. As a result, attempting this negation effectively wraps around and returns the original value. This is a known limitation and a key example of overflow behaviour in binary arithmetic. In programming or hardware, this could cause logic errors if not managed, so additional checks or wider bit lengths may be used when handling extremes.
Overflow in two’s complement addition occurs when the result of an operation exceeds the range that can be represented using the given number of bits. One reliable method for detecting overflow is to examine the carry into and out of the sign bit (the most significant bit). Overflow happens when the carry into the sign bit is different from the carry out. Another approach is to look at the signs of the operands and the result. If two positive numbers are added and the result is negative, overflow has occurred. Similarly, if two negative numbers are added and the result is positive, overflow has also occurred. For example, adding 01000000 (+64) and 01000000 (+64) in 8-bit gives 10000000, which is −128. This is a clear case of overflow because the expected result, 128, is outside the 8-bit range. Monitoring these conditions during arithmetic operations helps ensure that unexpected sign changes are caught and handled appropriately.
Two’s complement is designed so that subtraction can be handled using standard binary addition, eliminating the need for separate subtraction hardware. In this system, negative numbers are encoded in such a way that adding a negative value is equivalent to subtracting the corresponding positive value. This works because two’s complement representation allows binary addition to wrap around naturally due to modulo 2^n arithmetic. The structure ensures that carries and overflows are handled consistently, so only one addition circuit is required to process both addition and subtraction. For example, to calculate 10 − 4, you can add 10 and the two’s complement of 4. The hardware simply performs binary addition on the two bit patterns and outputs the result. This dual-purpose behaviour simplifies processor design, reduces hardware complexity, and increases speed. It’s one of the main reasons two’s complement is widely used in CPUs and digital systems.
Yes, extending two’s complement numbers to a higher bit-width while preserving their value is possible through a process called sign extension. This involves copying the most significant bit (the sign bit) into the new, higher-order bits of the extended number. If the MSB is 0 (positive), you pad the number with 0s on the left. If the MSB is 1 (negative), you pad it with 1s. This technique maintains the original value of the number because it preserves the weight of the sign bit. For example, the 4-bit two’s complement value 1101 (−3) can be sign-extended to 8 bits by adding four 1s at the front, resulting in 11111101, which is still −3 in 8-bit. Without sign extension, padding with 0s would change the value entirely. Sign extension is essential when performing operations on numbers of differing bit-widths or converting values between registers of different sizes in processors.
