Bus contention occurs when two or more components attempt to use the same bus simultaneously, causing data collisions and unpredictable behaviour. This is especially problematic on the data bus, which is bidirectional and used by both the CPU and other components for reading and writing data. If multiple devices try to place signals on the bus at once, the result can be corrupted data or even hardware damage. To prevent this, computer systems implement bus arbitration protocols. These protocols ensure that only one device controls the bus at a time. Common arbitration methods include daisy chaining, where devices are connected in series and access is passed along the chain, and centralised arbitration, where a controller decides which device can use the bus. Some systems also use tri-state logic, allowing devices to effectively disconnect from the bus when not in use. These measures help maintain signal integrity and avoid communication errors.

Handshaking is a protocol used to manage communication between components that operate asynchronously, meaning they do not share a common clock signal. It ensures that data is transferred only when both the sender and the receiver are ready. In a typical handshaking process, the sender begins by placing data on the bus and asserting a control signal such as "Data Ready." The receiver monitors this signal and, when ready to accept the data, responds with an "Acknowledge" signal. Once the acknowledgement is received, the sender removes the data from the bus and lowers the control signal. This method prevents data loss and timing errors that can occur when devices operate at different speeds. Handshaking is especially useful for slower peripherals that cannot keep up with the CPU’s pace. Although handshaking adds complexity and slightly increases the time taken for communication, it is essential for reliable data transfer in systems that do not rely solely on synchronous operation.

The control unit (CU) acts as the central coordinator within the CPU, managing the flow of data and instructions between the processor and other parts of the system. It interprets the fetched instruction and generates a series of timed control signals to execute it. These signals are sent over the control bus and instruct other components what to do and when. For example, during a read operation, the control unit sends out a "Read" signal and a "Memory Request" signal to ensure that data is retrieved from the correct memory location. It also synchronises operations with the system clock, ensuring that each step of the instruction cycle occurs at the right time. In more complex CPUs, the control unit may use microprogramming or hardwired logic to generate sequences of control signals. It ensures that the address, data, and control buses are used correctly and in a coordinated manner, preventing conflicts or incorrect operations.

Expanding the number of devices using memory-mapped I/O introduces several challenges. First, each device requires a unique memory address range, which reduces the total number of addresses available for main memory. This can be problematic in systems with limited address space, such as those with an 8-bit or 16-bit address bus, where the total number of addressable locations is 256 or 65,536 respectively. Allocating addresses to many devices may lead to fragmentation or inefficient use of the address space. Second, as more devices are added, the complexity of decoding addresses increases. The system must be able to accurately detect whether a given address corresponds to RAM, ROM, or a specific I/O device. Address decoders must become more sophisticated and may introduce latency. Additionally, if two devices are mistakenly assigned overlapping address ranges, data corruption or unpredictable behaviour may occur. To avoid these issues, careful address planning and clear documentation are essential in memory-mapped I/O systems.

Devices in a computer system operate at different speeds, and ensuring successful communication between fast and slow devices requires various techniques. One common approach is the use of wait states, where the CPU inserts additional clock cycles during which it pauses execution to give slower devices time to respond. This ensures that the CPU doesn’t read or write data before the device is ready. Another method is buffering, where temporary storage (buffers) is used to hold data being transferred to or from slow devices, allowing the CPU to continue executing other instructions while the transfer completes. For asynchronous devices, handshaking protocols are often used to manage timing, ensuring both sender and receiver are ready before data exchange occurs. Some systems also include interrupts, where slower devices signal the CPU only when they’re ready, avoiding unnecessary checking. These mechanisms ensure data integrity and smooth operation, even when components operate at drastically different speeds.